1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection circuitry for an IC (integrated circuit) input, and more particularly to controlling the load capacitance of the protection circuitry on the input.
2. Background Information
Integrated circuits are susceptible to and may be destroyed by ESD pulses. It is known that such ESD pulses may emanate from several sources, one primary source being from a human touching the IC. But, other sources may produce destructive ESD events. Such ESD pulses may include thousands of voltage and amperes of current that exist for a hundred nanoseconds or so. ESD events (defined as discharges or pulses) typically drive current into the IC, but may also sink current from the IC. Protection from both types is provided.
Protection devices and circuits have been developed over a number of years that have provided reliable protection. Some of these protective circuits use voltage limiting devices that discharge the ESD pulse before the pulse travels into the IC. U.S. Pat. No. 5,940,258('258) illustrates a protection circuit that is functionally reproduced in FIG. 1.
In FIG. 1 a positive going ESD pulse occurring on the pad 1 is capacitively coupled 4 to the gates of NMOS transistors Q1 and Q2 that share a common substrate. Q2 is smaller than Q1 and turns on quicker and produces a voltage across R1 and the common substrate. This substrate voltage helps Q1 turn on more fully, thereby discharging the ESD pulse.
However, a limitation of the '258 circuit and other prior art ESD protection circuits is that the circuits introduce a load capacitance on the pad that is sensitive to input voltage level. This sensitivity distorts an input signal and diminishes circuit performance.
Another prior art circuit is shown in U.S. Pat. No. 6,690,066. This patent improves upon the '258 patent by introducing a diode, D1, between the drain of Q1 and the pad of FIG. 1. The diode D1 isolates and minimizes the drain capacitance of Q1 with respect to the pad, and, importantly, the diode capacitance has a positive voltage coefficient that may be used to counter the negative voltage capacitance coefficient of Q1 and Q2. In this manner the capacitance load on the pad 2 may be made more constant and less sensitive to changing input signal voltages.
The '066 patent is directed to linearizing the ESD circuit capacitance, but does so with circuits that are only referenced to ground. The present invention linearizes the ESd capacitance while providing an ESd protection discharge path to both the power rail and to ground. The parallel paths improve ESD protection when, for example, the ground is path is insufficient to discharge the ESD pulse. Moreover, having the present inventive ESD circuit referenced to Vcc allows it to be designed more tolerant of overvoltages on the power rail.
Typical IC circuits lie between a power rail and ground, but, as known to those skilled in the art, a circuit may lie between two voltage levels, the higher may be designated as Vdd and the lower as Vss. In this disclosure, Vcc represents the higher voltage level and ground represents the lower voltage level.